1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to a monolithic surface mount semiconductor device and fabrication method.
2. Description of the Prior Art
Some of the main issues driving component packaging today include thermal and electrical performance, real estate constraints (i.e., package size) and manufacturing cost. With integrated circuit (IC) geometries shrinking well into the sub-micron level, and operating frequencies in the gigahertz range, attention has focused on the evolution of advanced packaging technologies to address the numerous issues now plaguing diode, transistor and IC designers. Ranging from thermal problems, to parasitic interference, to inductive losses, these issues have created a technological bottleneck which has made packaging technology a crucial concern.
One of the basic limitations of semiconductor devices is the dissipation of heat generated during operation of the device. This heat must be transferred to some thermal sink without causing excessive temperature rise within the device. Such excessive temperatures can cause partial or total device failure, and generally degrades the overall reliability of the device. The ability to dissipate heat places an upper bound on the maximum allowable power dissipation or ambient temperature range of operation of the device.
Where speed or power dissipation is not an issue, conventional plastic packages (e.g., dual-in-line package, surface mount, etc.), which are typically non-hermetic and made of injection-molded epoxy compounds, are employed in the semiconductor industry due to their low cost. Plastic packages, however, inherently have higher parasitic capacitance and lower thermal conductivity, compared to other package types. Furthermore, conventional plastic package performance falls off or becomes widely erratic at higher frequencies (typically exceeding 1 gigahertz) due, at least in part, to variations in package parasitics (i.e., parasitic capacitance and inductance) from device to device. These and other disadvantages make standard plastic packages unsuitable for applications requiring high speed and high power dissipation.
Historically, where high speed and/or high power dissipation was a critical design requirement, expensive ceramic or metal can packages have been used, which generally exhibit lower parasitic capacitance, higher thermal conductivity and greater mechanical strength than plastic packages. Aside from a substantially increased cost over standard plastic packages, however, ceramic and metal packages have a further disadvantage of being bulkier than their plastic counterparts (i.e., larger in size), which is a detriment where circuit board real estate is scarce. Additionally, bonding wires, which connect the bond pads of the semiconductor device to the package pins, adds series inductance which severely degrades the high frequency performance of the device.
Driven by the need for smaller consumer products and lower manufacturing costs, there has been a trend to shrink die and package sizes of the circuit components. This is most evident, for example, in the cellular telephone market, which has been recently pushing operating frequencies into the gigahertz range while concurrently shrinking the product size to easily fit in a shirt pocket. Because integrated circuit technology has resulted in increased functionality, enabling more circuit elements to be fabricated on the same semiconductor die, more heat is generated per unit volume within the smaller package footprint. Higher clock frequencies have further challenged the heat dissipation and speed capability of conventional package designs.
Although some heat generated by the semiconductor die is conveyed to the outside of the device package through the mold compound, the primary heat flow paths for a standard leadframe package are through the package leads themselves (typically made of copper). Unfortunately, however, conventional package leads and bond wires add significant amounts of parasitic inductance to the circuit. Although the length of the bond wires may be less for smaller package arrangements, the parasitic inductance associated with these bond wires is still considerably significant at such frequencies, for example, in the gigahertz range. Therefore, high frequency performance remains substantially impaired. High-speed performance, high power dissipation and small package size represent conflicting design requirements. Thus far, conventional integrated circuit packaging technology has failed to concurrently fulfill these important characteristics.
There are other various problems associated with conventional packaging technologies. For example, dwindling printed circuit board space has pressured semiconductor manufacturers to produce components having a smaller footprint (i.e., external package dimensions). Furthermore, quality performance and reliability problems, and costly delays associated with offshore manufacturing (e.g., assembly and packaging), are additional concerns that prior art packaging technologies have failed to alleviate.
By focusing on only a single specific design problem, rather than addressing multiple problems simultaneously, prior art packaging technologies have exacerbated other equally crucial problems. Accordingly, there remains a need in the prior art to provide a semiconductor device chip integrated into a packaging arrangement, in combination, that, among other things, is capable of high frequency operation, that can more readily dissipate the heat generated by the integrated circuit, that is smaller in physical size, that utilizes conventional semiconductor fabrication technology and that has a relatively low manufacturing cost.